Pokemon Mini Hardware Reference


The pokemon mini has a 21 bit external address bus, 24 bit internal, with an external clock of 4.00mhz
The Minx processor (Custom Nintendo CPU) consists of a quazi 16bit ALU, 6 16 bit registers, and 12 8 bit registers.
The Minx processor uses 8bit instruction sizes, with immediate values of 8 or 16 bits. There are two special instructions (CE and CF) which alter the function of the next instruction.
The pokemon mini also includes a RTC EEPROM with 8192 bytes of total memory (a header is used to partition the space into 6 distinguishable blocks). Strangely enough, the first 4 bytes of the EEPROM are set to "GBMN", which can only be interpreted as "Gameboy mini". Perhaps this project was dumbed down as more of a marketing ploy rather than an actual game system.

Although the processor has a relatively high clock speed, the cpu itself appears to have an internal divider associated with the frequency, also, the processor does not seem to decern between ram and rom when it comes to speed. This probibly means that the addressing bus runs faster than the CPU itself, even when it is using the multiplexed cart bus! Strange but true.

For the instruction set, see the good things to know about table.

16 Bit Registers

Register Description
PC   Program cursor. If the MSB of PC is logical high, PC is extended to 23 bits with the upper 8 bits being equal to the value of V
SP Stack pointer, used primarily for PUSH / POP instructions, although there are opcodes to extend it's functionality
BA 16 bit arithmatic accumulator, usually the result of operations
HL Secondary accumulator and memory index. If used as a memory index, the value is extended to 24 bits using the I index register
X Memory address register 1, extended to 24 bits using XI
Y Memory address register 2, extended to 24 bits using YI

8 Bit Registers

Register Description
A Accumulator, generally used for arithmatic results. Also the low-order byte of BA
B Loop-count register, also the hi-order byte for BA
L General purpose register, also low-order byte for HL
H General purpose register, also high-order byte for HL
U Delayed jump bank. When a jump occurs, V is set to this value. Used to branch to extended locations in memory
V PC Banking register. Used to extend the program cursor to a 23 bit value, see PC's description
F Flags register, used to control CPU flow and stores arithmatic conditions
E Exception register. When enabled, it stores execution errors.
I Index register, used to extend immediate, N addressing and HL addressing to a 24 bit value
N Indexing register, when used as a memory address, it used as bits 15:8 of the address, I is 23:16, and and an 8bit immediate is used for the address
XI Used as the upper 8 bits of X when used as an memory address
YI Used as the upper 8 bits of Y when used as an memory address

Flags and Exceptions

Bit Flag field Exception field
0 Zero flag Exception 0
1 Carry flag Exception 1
2 Overflow flag Exception 2
3 Sign flag Divide by Zero
4 BCD decimal mode enable Enable exceptions
5 Low-mask mode enable Unknown
6 Interrupt disable Unknown
7 Interrupt branch Unknown



Setting Interrupt Disable to is a master disable. No IRQs can occur if this flag is set.
Interrupt branch is set to 1 by the CPU when it calls an IRQ, after pushing the flags. It can be used internally to detect if you are executing interrupt code.
X is known as X1 by the PokeMe team, and the address extension index (bank) is generally considered unnamed since it is always associated with this register.
Y is known as X2. Same rules apply as X1.
HL's extension register is generally considered unnamed, but I associate the name I, due to the fact that it's not limited to HL. the GC emulator internally associated this value with HL, presumably due to speed concerns.

Memory Map

Address Range Function
0x00000:0x00FFF BIOS Rom space, IRQ vectors are hardcoded here, and redirected to the cartridge
0x01000:0x012FF Frame Buffer
0x01300:0x0135F OAM Memory
0x01360:0x0145F Tile Map
0x01460:0x01FFF General Purpose Ram
0x02000:0x020FF Hardware Registers
0x02100:0xFFFFF Game rom, aligned to 0x0000. The first 8 1/16 k of rom is unavailable


Memory is wrapped at the 21 bit boundary, most likely, it wraps around to rom space, but this in unconfirmed. The cartridge bus only allows for 21 addressing bits, so the usefulness of this is limited. Hey, we do what we can for another 8.0625k of rom!

Good things to know about

Instruction Set The base instructions, these are the fastest and smallest instructions used on the processor
CE Instructions Contains lots of additional arithmatic, including multiplication, division, and shifting, and more!
CF Instructions Contains lots of additional movement instructions, mostly general purpose stuff
IRQ vectors Locations of IRQs (interrupts) and when they occur
Frame Buffer Description of the video frame buffer, the PM always renders what is in this buffer. Tile mode just renders here!
Tile Map A variable size array of tile indexes, see here for a more detailed description
OAM Memory Sprite attribute memory
Hardware Registers Controls external hardware, very important!
Game rom This is where game data is stored
Minimon My personal pokemon mini emulator project
Timing Hardware timing. Stuff like LCD refresh, etc.


As with most things, a lot of this has not been discovered yet, but we are working to discover it all as we go! Please feel free to e-mail me with sugestions, or make corrections.